Unless otherwise indicated, the foregoing is not admitted to be prior art to the claims recited herein and should not be construed as such.
Modern microprocessors and related digital electronics continue to require power supplies that are capable of supporting fast transient loading. Power supplies based on converters that operation in pulse width modulation (PWM) mode are a common design choice.
Fast transient buck regulators, for example, can be designed to respond to millivolts of change within nanoseconds. If the modulator component in a buck regulator is designed to respond quickly, the active modulating block (e.g., comparator, very fast error amplifier, etc.) can respond to disturbances resulting from the parasitic series inductance of the output capacitor, sometimes referred to as equivalent series inductance (ESL). Although a capacitor ESL exists in the output capacitor of any buck regulator design, lower frequency designs are generally not susceptible to this artifact of capacitor ESL. The effect becomes significant in buck regulators designed for high speed operation.
The disturbances arising from capacitor ESL manifest themselves as multiple pulses superimposed over a normal modulated switching waveform that drives the switching of the power transistors of the buck regulator. Resulting system level degradations include poor power efficiency due to increased switching losses, and poor noise performance.
Referring to FIG. 6, the output section of a buck converter is illustrated, showing the capacitor ESL. Capacitors are typically modeled with an equivalent series resistance (ESR) as well. For the purposes of this discussion, the ESR can be omitted to simplify the discussion without sacrificing technical accuracy. An inductor divider is formed between the primary buck inductor L and the capacitor ESL. Each time the switching node connecting the power transistors transitions between minimum and maximum voltage (e.g., ground potential and VDD), the voltage swing VSW seen at the switching nodes (typically several volts) will be divided down by the ratio of the inductances of the primary inductor L and the capacitor ESL. Each transition (step) at the switching node creates a corresponding transition of several millivolts in magnitude at the output voltage node. The inductor current changes slope based on the law of
  v  =      L    ×                            ⅆ          i                          ⅆ          t                    .      Since the capacitor ESL conducts the same AC current as the primary inductor L,
      ⅆ    i        ⅆ    t  of the capacitor ESL is the same as the primary inductor. Accordingly, the magnitude of the ESL-generated transition at the output node can be represented by:
            V      ESL        =                  V        SW            ×              ESL        L              ,    where ESL and L are respective inductance values of the capacitor ESL and the primary inductor.
The ESL transition at the output node, which feeds back as negative feedback into the switching controller, can cross over the reference signal that is used to generate the switching voltage. Waveforms 1 and 2 in FIG. 6 represent the waveforms of a slow response regulator, where the response time is greater than the ESL transitions.
By comparison, in a fast response regulator that is fast enough to respond to VESL, the ESL-generated negative feedback can result in oscillations in the switching voltage as the circuit tries to compensate for the transition. The oscillations continue until the reference signal level rises above the level of the ESL-generated artifact in the output node. This effect may be represented by waveforms 3 and 4 in FIG. 6.